triSYCL for Xilinx FPGA

Andrew Gozillon; Ronan Keryell; Lin-Ya Yu; Gauthier Harnisch; Paul Keir

triSYCL for Xilinx FPGA

Andrew Gozillon
, Ronan Keryell
, Lin-Ya Yu
, Gauthier Harnisch
, Paul Keir

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Abstract

Khronos SYCL is a C++ based open-source specification that aims to increase the programmability of heterogeneous architectures. Several SYCL implementations exist, with variations both in terms of conformance to the specification; as well as in the range of hardware they target. Intel recently contributed the first open-source feature-complete SYCL implementation to the LLVM compiler project. The triSYCL project is another open-source SYCL implementation which targets Xilinx FPGAs. We describe here initial work to combine components of the triSYCL implementation with Intel's SYCL implementation, and provide details of the resulting updated compiler infrastructure for targeting the FPGA. We also highlight what is currently possible with the new hybrid triSYCL implementation alongside some interesting extensions for Xilinx FPGAs.

Original language	English
Title of host publication	Proceedings of the 2020 International Conference on High Performance Computing & Simulation (HPCS)
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	4
Publication status	Published - 22 Dec 2020
Event	The 2020 International Conference on High Performance Computing & Simulation - Barcelona, Spain Duration: 25 Jan 2021 → 29 Jan 2021

Conference

Conference	The 2020 International Conference on High Performance Computing & Simulation
Abbreviated title	HPCS 2020
Country/Territory	Spain
City	Barcelona
Period	25/01/21 → 29/01/21

Keywords

SYCL
Reconfigurable Computing
Clang
LLVM
FPGA
SPIR-V
HPC

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https://www.semanticscholar.org/paper/triSYCL-for-Xilinx-FPGA-Gozillon-Keryell/9cc921109fb5660d8651ddc6eaf3380768526384

Cite this

@inproceedings{7192b09be6824affb85712fb7ad07a02,

title = "triSYCL for Xilinx FPGA",

abstract = "Khronos SYCL is a C++ based open-source specification that aims to increase the programmability of heterogeneous architectures. Several SYCL implementations exist, with variations both in terms of conformance to the specification; as well as in the range of hardware they target. Intel recently contributed the first open-source feature-complete SYCL implementation to the LLVM compiler project. The triSYCL project is another open-source SYCL implementation which targets Xilinx FPGAs. We describe here initial work to combine components of the triSYCL implementation with Intel's SYCL implementation, and provide details of the resulting updated compiler infrastructure for targeting the FPGA. We also highlight what is currently possible with the new hybrid triSYCL implementation alongside some interesting extensions for Xilinx FPGAs.",

keywords = "SYCL, Reconfigurable Computing, Clang, LLVM, FPGA, SPIR-V, HPC",

author = "Andrew Gozillon and Ronan Keryell and Lin-Ya Yu and Gauthier Harnisch and Paul Keir",

year = "2020",

month = dec,

day = "22",

language = "English",

booktitle = "Proceedings of the 2020 International Conference on High Performance Computing \& Simulation (HPCS)",

publisher = "IEEE",

address = "United States",

note = "The 2020 International Conference on High Performance Computing \& Simulation, HPCS 2020 ; Conference date: 25-01-2021 Through 29-01-2021",

}

Gozillon, A, Keryell, R, Yu, L-Y, Harnisch, G & Keir, P 2020, triSYCL for Xilinx FPGA. in Proceedings of the 2020 International Conference on High Performance Computing & Simulation (HPCS). IEEE, Piscataway, NJ, The 2020 International Conference on High Performance Computing & Simulation, Barcelona, Spain, 25/01/21. <https://www.semanticscholar.org/paper/triSYCL-for-Xilinx-FPGA-Gozillon-Keryell/9cc921109fb5660d8651ddc6eaf3380768526384>

TY - GEN

T1 - triSYCL for Xilinx FPGA

AU - Gozillon, Andrew

AU - Keryell, Ronan

AU - Yu, Lin-Ya

AU - Harnisch, Gauthier

AU - Keir, Paul

PY - 2020/12/22

Y1 - 2020/12/22

N2 - Khronos SYCL is a C++ based open-source specification that aims to increase the programmability of heterogeneous architectures. Several SYCL implementations exist, with variations both in terms of conformance to the specification; as well as in the range of hardware they target. Intel recently contributed the first open-source feature-complete SYCL implementation to the LLVM compiler project. The triSYCL project is another open-source SYCL implementation which targets Xilinx FPGAs. We describe here initial work to combine components of the triSYCL implementation with Intel's SYCL implementation, and provide details of the resulting updated compiler infrastructure for targeting the FPGA. We also highlight what is currently possible with the new hybrid triSYCL implementation alongside some interesting extensions for Xilinx FPGAs.

AB - Khronos SYCL is a C++ based open-source specification that aims to increase the programmability of heterogeneous architectures. Several SYCL implementations exist, with variations both in terms of conformance to the specification; as well as in the range of hardware they target. Intel recently contributed the first open-source feature-complete SYCL implementation to the LLVM compiler project. The triSYCL project is another open-source SYCL implementation which targets Xilinx FPGAs. We describe here initial work to combine components of the triSYCL implementation with Intel's SYCL implementation, and provide details of the resulting updated compiler infrastructure for targeting the FPGA. We also highlight what is currently possible with the new hybrid triSYCL implementation alongside some interesting extensions for Xilinx FPGAs.

KW - SYCL

KW - Reconfigurable Computing

KW - Clang

KW - LLVM

KW - FPGA

KW - SPIR-V

KW - HPC

UR - https://ieeexplore.ieee.org/xpl/conhome/1800007/all-proceedings

M3 - Conference contribution

BT - Proceedings of the 2020 International Conference on High Performance Computing & Simulation (HPCS)

PB - IEEE

CY - Piscataway, NJ

T2 - The 2020 International Conference on High Performance Computing & Simulation

Y2 - 25 January 2021 through 29 January 2021

ER -

triSYCL for Xilinx FPGA

Abstract

Conference

Keywords

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