triSYCL for Xilinx FPGA

Andrew Gozillon, Ronan Keryell, Lin-Ya Yu, Gauthier Harnisch, Paul Keir

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

148 Downloads (Pure)

Abstract

Khronos SYCL is a C++ based open-source specification that aims to increase the programmability of heterogeneous architectures. Several SYCL implementations exist, with variations both in terms of conformance to the specification; as well as in the range of hardware they target. Intel recently contributed the first open-source feature-complete SYCL implementation to the LLVM compiler project. The triSYCL project is another open-source SYCL implementation which targets Xilinx FPGAs. We describe here initial work to combine components of the triSYCL implementation with Intel's SYCL implementation, and provide details of the resulting updated compiler infrastructure for targeting the FPGA. We also highlight what is currently possible with the new hybrid triSYCL implementation alongside some interesting extensions for Xilinx FPGAs.
Original languageEnglish
Title of host publicationProceedings of the 2020 International Conference on High Performance Computing & Simulation (HPCS)
Place of PublicationPiscataway, NJ
PublisherIEEE
Number of pages4
Publication statusAccepted/In press - 22 Dec 2020
EventThe 2020 International Conference on High Performance Computing & Simulation - Barcelona, Spain
Duration: 25 Jan 202129 Jan 2021

Conference

ConferenceThe 2020 International Conference on High Performance Computing & Simulation
Abbreviated titleHPCS 2020
Country/TerritorySpain
CityBarcelona
Period25/01/2129/01/21

Keywords

  • SYCL
  • Reconfigurable Computing
  • Clang
  • LLVM
  • FPGA
  • SPIR-V
  • HPC

Fingerprint

Dive into the research topics of 'triSYCL for Xilinx FPGA'. Together they form a unique fingerprint.

Cite this