Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank

Basant K. Mohanty, Somaya Al-Maadeed, Abbes Amira

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we present an efficient poly-phase decomposition scheme for implementation of 2-D non-separable filter bank. Poly-phase decomposition scheme offers multiplexing of filter bank computations or/and reduce the data clocking without affecting the overall throughput rate. Both these features can be used conveniently depending on resources availability or processor-technology. Time-multiplexing could be the choice for resource-constrained applications. Slower clocking rate could be chosen if processor-technology is the constraint. In that case, the design could be realized with cheaper and slower processor-technology. Time-multiplexed design needs proper data scheduling to perform filter bank computation interleavingly without data overlapping. Keeping this in mind, we have derived a systolic architecture for hardware realization of time-multiplexed filter bank where we have used novel data buffering scheme for the filter coefficients of the filter bank. Comparison result show that, the proposed structure involves almost J times less hardware resource than the non poly-phase filter bank structure and it provides the same throughput rate as the other, where is the filter bank size. The hardware saving is significant for large size filter banks like Gabor. The proposed structure could be a good candidate for efficient hardware implementation of non-separable filter bank used in various image processing applications such as biometrics systems.
Original languageEnglish
Title of host publication2013 8th IEEE Design and Test Symposium (IDT)
Subtitle of host publicationMarrakesh, Morocco, December 16-18, 2013
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Print)9781479935253
DOIs
Publication statusPublished - 2013
Externally publishedYes

Keywords

  • finite impulse response filters
  • hardware
  • registers
  • clocks
  • delays
  • computer architecture
  • multiplexing

Cite this

Mohanty, B. K., Al-Maadeed, S., & Amira, A. (2013). Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank. In 2013 8th IEEE Design and Test Symposium (IDT): Marrakesh, Morocco, December 16-18, 2013 (pp. 1-6). IEEE. https://doi.org/10.1109/IDT.2013.6727130