SYCL for Xilinx Versal ACAP AIE CGRA

Ronan Keryell, Andrew Gozillon, Gauthier Harnisch, Hyun Kwon, Ravikumar Chakaravarthy, Ralph Wittig

Research output: Contribution to conferencePosterpeer-review

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SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different backends.

Xilinx Versal ACAP is a new system-on-chip (SoC) device integrating various computing resources like various CPUs, an FPGA, a coarse-grain reconfigurable array (CGRA), etc. interconnected by different network-on-chip (NoC).

The AIE CGRA is an array of 400 VLIW DSP operating on 512-bit vectors with their own neighborhood distributed memory (32 KiB data, 16 KiB instructions).
We expose architectural details to the programmer through some SYCL extensions and extend SYCL with a geographical collective model.

The SYCL implementation targeting the AIE CGRA by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL and a new SYCL runtime from triSYCL.

The SYCL device compiler generates LLVM IR for the Synopsys ASIP CHESS compiler generating the AIE instructions.

The host runtime runs on the ARM A72 CPU of the ACAP and controls the CGRA through the Xilinx libxaiengine-v2 library.
Original languageEnglish
Publication statusPublished - 28 Apr 2021
EventIWOCL SYCLCon 2021: 9th International Workshop on OpenCL and SYCL - Online
Duration: 28 Apr 202129 Apr 2021 (Conference website.)


ConferenceIWOCL SYCLCon 2021
Abbreviated titleSYCLCon
Internet address


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