SYCL for Vitis 2020.2: SYCL & C++20 on Xilinx FPGA

Keyphrases

• Xilinx 100%
• Xilinx FPGA 100%
• Vitis 100%
• C++20 100%
• C + + 50%
• OpenCL 50%
• Open-source Implementation 50%
• Device Configuration 50%
• DPC++ 50%
• Alveo 50%
• Xilinx Vitis 50%
• LLVM IR 50%
• OneAPI 50%
• FPGA Device 50%

Computer Science

• Field Programmable Gate Arrays 100%
• Open Source 33%
• OpenCL 33%
• Back End 33%

Psychology

• Merging 100%