SYCL for Vitis 2020.2: SYCL & C++20 on Xilinx FPGA

Gauthier Harnisch, Andrew Gozillon, Ronan Keryell, Lin-Ya Yu, Ralph Wittig, Luc Forget

Research output: Contribution to conferencePosterpeer-review

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SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different back-ends. We present an experimental SYCL implementation targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL. The FPGA device configuration is generated by Xilinx Vitis 2020.2 fed with LLVM IR SPIR and Xilinx XRT is used as a host OpenCL API too control the device.
Original languageEnglish
Publication statusAccepted/In press - 27 Apr 2021
EventIWOCL SYCLCon 2021: 9th International Workshop on OpenCL and SYCL - Online
Duration: 28 Apr 202129 Apr 2021 (Conference website.)


ConferenceIWOCL SYCLCon 2021
Abbreviated titleSYCLCon
Internet address


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