SYCL for Vitis 2020.2: SYCL & C++20 on Xilinx FPGA

Gauthier Harnisch; Andrew Gozillon; Ronan Keryell; Lin-Ya Yu; Ralph Wittig; Luc Forget

SYCL for Vitis 2020.2: SYCL & C++20 on Xilinx FPGA

Gauthier Harnisch, Andrew Gozillon, Ronan Keryell, Lin-Ya Yu, Ralph Wittig, Luc Forget

School of Computing, Engineering and Physical Sciences

Research output: Contribution to conference › Poster › peer-review

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Abstract

SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different back-ends. We present an experimental SYCL implementation targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL. The FPGA device configuration is generated by Xilinx Vitis 2020.2 fed with LLVM IR SPIR and Xilinx XRT is used as a host OpenCL API too control the device.

Original language	English
Publication status	Accepted/In press - 27 Apr 2021
Event	IWOCL SYCLCon 2021: 9th International Workshop on OpenCL and SYCL - Online Duration: 28 Apr 2021 → 29 Apr 2021 https://www.iwocl.org/ (Conference website.)

Conference

Conference	IWOCL SYCLCon 2021
Abbreviated title	SYCLCon
Period	28/04/21 → 29/04/21
Internet address	https://www.iwocl.org/ (Conference website.)

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2021 04 27 Harnisch et al SYCL acceptedAccepted author manuscript, 953 KB

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@conference{b878164d360f4f5d9782f191eef4fb85,

title = "SYCL for Vitis 2020.2: SYCL & C++20 on Xilinx FPGA",

abstract = "SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different back-ends. We present an experimental SYCL implementation targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel{\textquoteright}s oneAPI DPC++ with some LLVM passes from triSYCL. The FPGA device configuration is generated by Xilinx Vitis 2020.2 fed with LLVM IR SPIR and Xilinx XRT is used as a host OpenCL API too control the device.",

author = "Gauthier Harnisch and Andrew Gozillon and Ronan Keryell and Lin-Ya Yu and Ralph Wittig and Luc Forget",

year = "2021",

month = apr,

day = "27",

language = "English",

note = "IWOCL SYCLCon 2021 : 9th International Workshop on OpenCL and SYCL, SYCLCon ; Conference date: 28-04-2021 Through 29-04-2021",

url = "https://www.iwocl.org/",

}

TY - CONF

T1 - SYCL for Vitis 2020.2

T2 - IWOCL SYCLCon 2021

AU - Harnisch, Gauthier

AU - Gozillon, Andrew

AU - Keryell, Ronan

AU - Yu, Lin-Ya

AU - Wittig, Ralph

AU - Forget, Luc

PY - 2021/4/27

Y1 - 2021/4/27

N2 - SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different back-ends. We present an experimental SYCL implementation targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL. The FPGA device configuration is generated by Xilinx Vitis 2020.2 fed with LLVM IR SPIR and Xilinx XRT is used as a host OpenCL API too control the device.

AB - SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different back-ends. We present an experimental SYCL implementation targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL. The FPGA device configuration is generated by Xilinx Vitis 2020.2 fed with LLVM IR SPIR and Xilinx XRT is used as a host OpenCL API too control the device.

UR - https://www.iwocl.org/iwocl-2021/conference-program/#program-tech-talk

M3 - Poster

Y2 - 28 April 2021 through 29 April 2021

ER -

SYCL for Vitis 2020.2: SYCL & C++20 on Xilinx FPGA

Abstract

Conference

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