SYCL is a single-source C++ DSL targeting a large variety of accelerators in a unified way by using different back-ends. We present an experimental SYCL implementation targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL. The FPGA device configuration is generated by Xilinx Vitis 2020.2 fed with LLVM IR SPIR and Xilinx XRT is used as a host OpenCL API too control the device.
|Publication status||Accepted/In press - 27 Apr 2021|
|Event||IWOCL SYCLCon 2021: 9th International Workshop on OpenCL and SYCL - Online|
Duration: 28 Apr 2021 → 29 Apr 2021
https://www.iwocl.org/ (Conference website.)
|Conference||IWOCL SYCLCon 2021|
|Period||28/04/21 → 29/04/21|