### Abstract

Original language | English |
---|---|

Pages (from-to) | 120-133 |

Journal | IEEE Transactions on Circuits and Systems I-regular Papers |

Volume | 61 |

Issue number | 1 |

DOIs | |

Publication status | Published - Jan 2014 |

### Keywords

- Block processing
- 2-dimensional (2-D) finite impulse response (FIR)
- digital filters
- VLSI architecture

### Cite this

*IEEE Transactions on Circuits and Systems I-regular Papers*,

*61*(1), 120-133. https://doi.org/10.1109/TCSI.2013.2265953

}

*IEEE Transactions on Circuits and Systems I-regular Papers*, vol. 61, no. 1, pp. 120-133. https://doi.org/10.1109/TCSI.2013.2265953

**Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters.** / Mohanty, Basant K.; Meher, Pramod K.; Al-Maadeed, Somaya; Amira, Abbes.

Research output: Contribution to journal › Article

TY - JOUR

T1 - Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters

AU - Mohanty, Basant K.

AU - Meher, Pramod K.

AU - Al-Maadeed, Somaya

AU - Amira, Abbes

PY - 2014/1

Y1 - 2014/1

N2 - We have analyzed memory footprint and combinational complexity to arrive at a systematic design strategy to derive area-delay-power-efficient architectures for two-dimensional (2-D) finite impulse response (FIR) filter. We have presented novel blockbased structures for separable and non-separable filters with less memory footprint by memory sharing and memory-reuse along with appropriate scheduling of computations and design of storage architecture. The proposed structures involve times less storage per output (SPO), and nearly times less energy consumption per output (EPO) compared with the existing structures, where is the input block-size. They involve times more arithmetic resources than the best of the corresponding existing structures, and produce times more throughput with less memory band-width (MBW) than others. We have also proposed separate generic structures for separable and non-separable filter-banks, and a unified structure of filter-bank constituting symmetric and general filters. The proposed unified structure for 6 parallel filters involves nearly times moremultipliers, timesmore adders, less registers than similar existing unified structure, and computes times more filter outputs per cycle with times less MBW than the existing design, where is FIR filter size in each dimension. ASIC synthesis result shows that for filter size (4 x 4), input-block size, and image-size (512 x 512), proposed block-based non-separable and generic non-separable structures, respectively, involve 5.95 times and 11.25 times less area-delay-product (ADP), and 5.81 times and 15.63 times less EPO than the corresponding existing structures. The proposed unified structure involves 4.64 times less ADP and 9.78 times less EPO than the corresponding existing structure.

AB - We have analyzed memory footprint and combinational complexity to arrive at a systematic design strategy to derive area-delay-power-efficient architectures for two-dimensional (2-D) finite impulse response (FIR) filter. We have presented novel blockbased structures for separable and non-separable filters with less memory footprint by memory sharing and memory-reuse along with appropriate scheduling of computations and design of storage architecture. The proposed structures involve times less storage per output (SPO), and nearly times less energy consumption per output (EPO) compared with the existing structures, where is the input block-size. They involve times more arithmetic resources than the best of the corresponding existing structures, and produce times more throughput with less memory band-width (MBW) than others. We have also proposed separate generic structures for separable and non-separable filter-banks, and a unified structure of filter-bank constituting symmetric and general filters. The proposed unified structure for 6 parallel filters involves nearly times moremultipliers, timesmore adders, less registers than similar existing unified structure, and computes times more filter outputs per cycle with times less MBW than the existing design, where is FIR filter size in each dimension. ASIC synthesis result shows that for filter size (4 x 4), input-block size, and image-size (512 x 512), proposed block-based non-separable and generic non-separable structures, respectively, involve 5.95 times and 11.25 times less area-delay-product (ADP), and 5.81 times and 15.63 times less EPO than the corresponding existing structures. The proposed unified structure involves 4.64 times less ADP and 9.78 times less EPO than the corresponding existing structure.

KW - Block processing

KW - 2-dimensional (2-D) finite impulse response (FIR)

KW - digital filters

KW - VLSI architecture

U2 - 10.1109/TCSI.2013.2265953

DO - 10.1109/TCSI.2013.2265953

M3 - Article

VL - 61

SP - 120

EP - 133

JO - IEEE Transactions on Circuits and Systems I-regular Papers

JF - IEEE Transactions on Circuits and Systems I-regular Papers

SN - 1549-8328

IS - 1

ER -