Abstract
In this paper we present a novel hardware architecture for reconstruction of signals in compressed sensing. The proposed architecture is based on the orthogonal matching pursuit (OMP) algorithm which has been modeled with Simulink and implemented on FPGA using Xilinx system generator. The main aim is to optimize both area and execution time. The execution time is reduced by exploiting parallelism inside each kernel, where the area is reduced by reusing several operators such as matrix vector multiplication. Hardware implementation on the Virtex5 FPGA has shown excellent results compared to existing implementations. Moreover, our solution achieves a speedup of 38 compared to a software solution on the Intel core duo CPU.
| Original language | English |
|---|---|
| Title of host publication | 11th International Conference on Information Science, Signal Processing and their Applications (ISSPA), 2012 |
| Place of Publication | Piscataway, NJ |
| Publisher | IEEE |
| Pages | 1336-1340 |
| Number of pages | 5 |
| ISBN (Print) | 9781467303811 |
| DOIs | |
| Publication status | Published - 24 Sept 2012 |
| Externally published | Yes |
Keywords
- compressed sensing
- digital signal processing chips
- field programmable gate arrays
- matrix multiplication
- signal reconstruction
- vectors
- Computer architecture
- Hardware
- Kernel
- Matching pursuit algorithms
- Matrix decomposition
- Symmetric matrices
- Vectors