FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration

Keyphrases

• Face Recognition 100%
• Field Programmable Gate Arrays 100%
• Array-based 100%
• Discrete Wavelet Transform 100%
• Intellectual Property Core 100%
• Partial Reconfiguration 100%
• Coefficient Selection 50%
• Construction Approach 25%
• Consumption Rate 25%
• Performance Analysis 25%
• Hardware Implementation 25%
• Maximum Frequency 25%
• Haar Wavelet Transform 25%
• Suitable Method 25%
• Feature Selection 25%
• Feature Optimization 25%
• Feature Extraction 25%
• Wavelet Transform Coefficient 25%
• Feature Vector Construction 25%
• Wavelet Filter 25%
• Feature Threshold 25%
• Recognition Accuracy 25%
• Wavelet 25%
• Recognition-based 25%
• Selection Thresholds 25%
• Area Consumption 25%
• Face Recognition System 25%
• Virtex-5 FPGA 25%
• Feature Filtering 25%
• Threshold Selection 25%
• Two-dimensional Haar Wavelets 25%
• Reconfiguration Process 25%

Computer Science

• Face Recognition 100%
• Wavelet Transforms 100%
• Reconfiguration 100%
• Field Programmable Gate Arrays 100%
• Feature Extraction 40%
• Construction Approach 20%
• Hardware Implementation 20%
• Performance Analysis 20%
• Feature Selection 20%
• Feature Vector 20%
• Recognition Accuracy 20%
• Transform Coefficient 20%
• Experimental Result 20%
• Area Power Consumption 20%
• Recognition System 20%
• Block Transform 20%

Engineering

• Field Programmable Gate Arrays 100%
• Intellectual Property Core 100%
• Partial Reconfiguration 100%
• Feature Extraction 66%
• Feature Vector 33%
• Recognition Accuracy 33%
• Electric Power Utilization 33%
• Two Dimensional 33%
• Experimental Result 33%
• Performance Analysis 33%
• Block Transform 33%