In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p(2)), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.
- Finite Ridgelet Transform
- Finite Radon Transform
- Image processing
Chandrasekaran, S., Amira, A., Minghua, S., & Bermak, A. (2008). An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform. Journal of Real-Time Image Processing, 3(3), 183-193. https://doi.org/10.1007/s11554-008-0081-1