Keyphrases
Single-path Delay Feedback
100%
Implementation on FPGA
100%
MIMO-OFDM
100%
Fast Fourier Transform
100%
Radix-2
100%
FPGA Implementation
20%
Proposed Architecture
20%
Feedback Method
20%
Architecture-centric
20%
FPGA Resources
20%
Multiplier Technique
20%
Hardware Efficiency
20%
FPGA Hardware
20%
Butterfly Model
20%
Parallel Processing
20%
Control Signal
20%
Utilization Rate
20%
Space Resources
20%
Hardware Architecture
20%
Radix-2 Butterfly
20%
Xilinx System Generator
20%
Virtex-5 FPGA
20%
Binary Counter
20%
Resource Saving
20%
Computer Science
Fast Fourier Transform
100%
MIMO-OFDM Dual-Functional Radar-Communication Systems
100%
radix 2
100%
Field Programmable Gate Arrays
100%
Presented Approach
12%
Data Stream
12%
Parallel Processing
12%
Control Signal
12%
Orthogonal Frequency Division Multiplexing
12%
Hardware Architecture
12%
Computer Hardware
12%
Engineering
Field Programmable Gate Arrays
100%
Feedback Delay
100%
Multiple-Input Multiple-Output
100%
Fast Fourier Transform
100%
Realization
12%
Orthogonal Frequency Division Multiplexing
12%
Control Signal
12%
Data Stream
12%