An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA

M. Dali, R. M. Gibson, A. Amira, A. Guessoum, N. Ramzan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a Single-path Delay Feedback (SDF) architecture for implementing a Fast Fourier Transform (FFT) processor on FPGA for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing. An FPGA resource efficient and shared multiplier technique for parallel processing of two and four data streams is demonstrated and utilized for realization within the presented SDF architecture based on a radix-2 butterfly model. The presented approach allows significant utilization efficiency of FPGA hardware-based multiplier elements opposed to a relative 50% less efficiency within conventional radix-2 SDF FPGA implemented techniques. The FPGA implementation demonstrated significant FPGA space resource savings compared to conventional radix-2 SDF methods and has been evaluated with other relative hardware architecture techniques. Additionally, the presented architecture is suitable for implementing and scaling to any FFT size N in correspondence with N = 2m. Furthermore, the proposed architecture is easily controlled through binary counter control signals. The presented architectures have been designed with Xilinx System Generator, realized and evaluated on a Virtex-5 FPGA XC5VSX240T-2FF1738 device.
Original languageEnglish
Title of host publicationNASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015
PublisherIEEE
Pages1-7
Number of pages7
ISBN (Print)9781467375016
DOIs
Publication statusPublished - 2015

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Keywords

  • MIMO communication
  • OFDM modulation
  • fast Fourier transforms
  • field programmable gate arrays
  • multiplying circuits
  • parallel processing
  • telecommunication computing
  • FFT processor
  • FPGA hardware-based multiplier elements
  • FPGA space resource savings
  • MIMO-OFDM radix-2
  • SDF architecture
  • Virtex-5 FPGA XC5VSX240T-2FF1738 device
  • Xilinx system generator
  • binary counter control signals
  • data streamsfast Fourier transform
  • multiple input multiple output orthogonal frequency division multiplexing
  • radix-2 butterfly model
  • shared multiplier technique
  • single-path delay feedback FFT
  • single-path delay feedback architecture
  • Delays
  • Hardware
  • Read only memory
  • Registers
  • Table lookup
  • fast Fourier transform (FFT)
  • multiple input multiple output (MIMO)
  • orthogonal frequency division multiplexing (OFDM)
  • single-path delay feedback (SDF)

Cite this

Dali, M., Gibson, R. M., Amira, A., Guessoum, A., & Ramzan, N. (2015). An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA. In NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015 (pp. 1-7). IEEE. https://doi.org/10.1109/AHS.2015.7231171