A High Speed Configurable FPGA Architecture For K-mean Clustering

Jithin Sankar Sankaran Kutty; Farid Boussaid; Abbes Amira

doi:10.1109/ISCAS.2013.6572215

A High Speed Configurable FPGA Architecture For K-mean Clustering

Jithin Sankar Sankaran Kutty, Farid Boussaid, Abbes Amira

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.

Original language	English
Title of host publication	2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Publisher	IEEE
Pages	1801-1804
ISBN (Print)	978-1-4673-5760-9
DOIs	https://doi.org/10.1109/ISCAS.2013.6572215
Publication status	Published - 2013

Publication series

Name	IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4302

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10.1109/ISCAS.2013.6572215

Cite this

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title = "A High Speed Configurable FPGA Architecture For K-mean Clustering",

abstract = "This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.",

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A High Speed Configurable FPGA Architecture For K-mean Clustering. / Kutty, Jithin Sankar Sankaran; Boussaid, Farid; Amira, Abbes.
2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). IEEE, 2013. p. 1801-1804 (IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Amira, Abbes

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AB - This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.

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DO - 10.1109/ISCAS.2013.6572215

M3 - Conference contribution

SN - 978-1-4673-5760-9

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BT - 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

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A High Speed Configurable FPGA Architecture For K-mean Clustering

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