A High Speed Configurable FPGA Architecture For K-mean Clustering

Jithin Sankar Sankaran Kutty, Farid Boussaid, Abbes Amira

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.
Original languageEnglish
Title of host publication2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
PublisherIEEE
Pages1801-1804
ISBN (Print)978-1-4673-5760-9
DOIs
Publication statusPublished - 2013

Publication series

NameIEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4302

Cite this

Kutty, J. S. S., Boussaid, F., & Amira, A. (2013). A High Speed Configurable FPGA Architecture For K-mean Clustering. In 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) (pp. 1801-1804). (IEEE International Symposium on Circuits and Systems). IEEE. https://doi.org/10.1109/ISCAS.2013.6572215